(1) Field of the Invention
The present invention relates to the fabrication of semiconductor devices on substrates, and more particularly relates to a method for making local metal interconnections that also improves the electrical conductivity of the polysilicon gate electrodes for field effect transistors (FETs) while providing low contact resistance to the underlying silicon substrate.
(2) Description of the Prior Art
Field effect transistors (FETs) are used in the semiconductor industry for Ultra Large Scale Integration (ULSI) circuits. These FETs are commonly formed using patterned conductively doped polysilicon layers for the gate electrodes and diffused self-aligned doped areas in the substrate adjacent to the gate electrodes for the source/drain areas. The polysilicon layers and the source/drain areas, even though conductively doped, have more electrical resistance than metal or metal silicide layers. This higher resistance is generally undesirable because it increases the RC (resistancexc3x97capacitance) time delay of the circuit and reduces circuit performance (speed). Therefore, it is a common practice in the industry to use metal silicide on the gate electrodes and local interconnections to improve the circuit performance.
One conventional method of forming the FETs with silicide gate electrodes and source/drain areas is to form the gate electrodes by patterning a multilayer of doped polysilicon, a metal silicide, and a cap oxide layer over the device areas. The gate electrodes are then used as a diffusion or implant barrier mask to form self-aligned lightly doped source/drain areas in the substrate adjacent to the sides of the gate electrodes. Sidewall insulating spacers are formed on the gate electrode sidewalls and a second implant, aligned to the sidewall spacers, is used to form the source/drain contact areas. A metal is deposited and annealed (sintered) to form the silicide source/drain contact areas with low resistance. However, this requires additional etching steps to form the gate electrodes in the multilayer of oxide, silicide, and polysilicon, which also requires reasonably vertical sidewalls for forming the sidewall spacers.
Another method which saves processing steps is the self-aligned silicide (salicide) process in which both the silicide gate electrodes and source/drain areas are made at the same time. In this method the gate electrodes are formed from a single doped polysilicon layer, and after forming insulating sidewall spacers, a single metal, such as titanium (Ti), is deposited and annealed to concurrently form the silicide source/drain areas and silicide gate electrodes. The unreacted Ti on the oxide sidewall spacers and on other oxide surfaces is removed to electrically isolate the silicide source/drain areas from the silicide gate electrodes.
However, as these polysilicon and polycide lines are reduced in width to allow higher circuit density for future integrated circuits, the resistance of the local interconnecting lines (including the gate electrodes) dramatically increases and circuit performance is diminished.
Several methods have been reported in the literature for reducing the polysilicon resistance by forming silicide on the FET gate electrodes and local interconnections.
For example, in U.S. Pat. No. 5,683,941 Kao teaches a method for making a self-aligned silicide on the patterned polysilicon using an overlying insulating layer that is planarized, and then etched back to expose the polysilicon. A metal layer is deposited and reacted with the exposed polysilicon to form the self-aligned polycide pattern. A method for making back-gate contacts for FETs on a silicon-on-insulator (SOI) substrate is described by Chan et al. in U.S. Pat. No. 5,610,083. The method chemically-mechanically polishes back an overlying insulating layer to a polysilicon contact for making electrical contact to the substrate, while concurrently forming the FETs. The method does not address local interconnections. Another method for improving the sheet resistance of an integrated circuit device gate is described by Givens et al. in U.S. Pat. No. 5,268,330. In this invention an insulating layer (doped SiO2) is polished back to a passivation layer (Si3N4) over the gate electrode. The passivation layer is removed over the gate electrode and a conducting material, such as tungsten, is deposited to make contact to the gate electrode to improve the sheet resistance. However, the invention does not describe the formation of improved metal local interconnections and improved transistor performance.
However, there is still a need in the semiconductor industry to fabricate local interconnections with improved electrical conductivity and improved transistor performance on future integrated circuits, where linewidths of the interconnections will be submicron in dimensions.
It is therefore a principal object of this invention to form local metal interconnections while improving the contact resistance to the substrate and improving the electrical conductivity of a patterned polysilicon layer that is used to form the FET gate electrodes.
It is another object of this invention to provide these improved contacts and FETs by selectively removing the cap insulating layer over the patterned polysilicon layer that also forms the FET gate electrodes.
Still another objective is to use the patterned metal layer for making the metal interconnections to form metal contacts in the insulating layer on the substrate to further reduce contact resistance.
Another object of this invention is to provide a simple and manufacturable process.
In accordance with the objects of the invention, a method for fabricating improved metal interconnections which also reduces the resistance of the patterned polysilicon layer that also forms the gate electrodes for the FETs. Also, the method concurrently forms metal contacts to the substrate in the insulating layer over the substrate which reduces contact resistance. Although the method is described for an N-channel FET on a P doped substrate, the method also applies to forming P-channel FETs on N doped substrates. Also, the process is compatible with making both P-channel and N-channel FETs, respectively, on doped N-wells and P-wells formed on and in the substrate.
The objectives described above are achieved by providing a semiconductor substrate, such as a single-crystal silicon doped with a P-type dopant, such as boron. Field OXide (FOX) regions are formed in and on the substrate to surround and electrically isolate device areas. The FOX is formed by shallow trench isolation (STI), as commonly used in the industry, and the STI is made planar with the substrate surface. After forming the STI, a gate oxide is formed, for example by thermal oxidation, over the device areas for the FETs. A conductively doped polysilicon layer is deposited on the substrate using low-pressure chemical vapor deposition (LPCVD) and is doped with a conductive dopant such as arsenic (As) or phosphorus (P) using ion implantation. Next a first insulating layer composed of silicon nitride (Si3N4) is deposited by low-pressure chemical vapor deposition (LPCVD) on the polysilicon layer. The first insulating layer and the polysilicon layer are patterned using a photoresist mask and anisotropic plasma etching. The polysilicon is patterned to form gate electrodes over the device areas and form portions of the local interconnections over the field oxide isolation regions. Lightly doped source/drain areas are formed next by ion implanting an N type dopant adjacent and aligned to the gate electrodes of the N-channel FET. A conformal second insulating layer composed of silicon oxide (SiO2) is deposited by CVD over the gate electrodes and is anisotropically etched back to form sidewall spacers on the sidewalls of the gate electrodes. Source/drain contact areas are then formed by ion implantation adjacent to the sidewall spacers. A third insulating layer composed of SiO2 is deposited on the substrate and is chemically-mechanically polished back to the first insulating layer (Si3N4) to form a planar surface. By the method of this invention, the Si3N4 first insulating layer is selectively removed over the patterned polysilicon layer to form recesses in the third insulating layer. The Si3N4 is selectively removed using, for example, a hot phosphoric acid solution while leaving the second and the third insulating layers essentially unetched. Next, contact openings are etched in the third insulating layer to the substrate using a photoresist mask and anisotropic etching. A blanket metal layer having high electrical conductivity is deposited to fill the contact openings and the recesses in the third insulating layer and to form an essentially planar layer over the substrate. For example, the metal layer can be composed of a barrier layer, such as titanium/titanium nitride (Ti/TiN), and a good electrical conductor such as tungsten, copper, aluminum, platinum, silver, palladium, or the like. Also by the method of this invention, the metal layer is patterned using a photoresist mask and anisotropic plasma etching to complete the local metal interconnections while leaving portions of the metal in the recesses to improve the electrical conductivity of the patterned polysilicon layer.
By a second embodiment of this invention, an additional photoresist mask is used to pattern the Si3N4 first insulating layer leaving portions over the patterned polysilicon layer to serve as crossovers for the patterned metal local interconnections. The Si3N4 can be etched using plasma etching in a gas that etches Si3N4 selectively.